synchronization - Verilog Falling Edge Detection -


i writing verilog code uart implemented on fpga, , have trouble synchronizing start bit of bytes after first one.

my manager suggested synchronize received signal , use kind of interrupt mean of communicating fsm start has been recognized.

i have read techniques rising edge detection, , feel this:

module startdetectionunit (     input clk, state, signal_in,     output trigger     );         reg signal_d;      @(posedge clk)         begin             signal_d <= signal_in;         end     assign trigger = signal_in & (!signal_d);  endmodule

in understanding, description detects rising edge, not falling edge, "start" logic '0' in rs-232 communications.

plus, want assign flag when in idle state [hardcoded 000] doing crazy gating on final assignments sounds non-hardwareish me.

tldr, 2 issues

  1. detecting generic falling edge of asynchronous input signal
  2. doing in single, specific state of fsm

thanks bunch, i'm new verilog , kinda-new hdl'ing

if signal signal_in come outside of design not synchronized correctly. in design using 1 d-latch, 2 required.

reg signal_d; @(posedge clk)     begin         signal_d <= signal_in;     end

this synthesize 1 d-latch. synchronize signal correctly have declare second signal 2 d-latch instantiation:

reg signal_d; reg signal_sync; @(posedge clk)     begin         signal_d <= signal_in;         signal_sync <= signal_d;     end

and signal_d should not used in design. make edge detection have declare third signal :

reg signal_d; reg signal_sync; reg signal_sync_old; @(posedge clk)     begin         signal_d <= signal_in;         signal_sync <= signal_d;         signal_sync_old <= signal_sync;     end

and falling edge detection :

assign trigger = signal_sync_old & (!signal_sync);

a website more information synchronization : https://www.doulos.com/knowhow/fpga/synchronisation/

as understand, signal 'state' coded in 3 bits, can :

assign trigger = (state == 3'b000) ? (signal_sync_old & (!signal_sync)):0;

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