Recommended order of input and output ports in Verilog module declaration -


being new verilog noticed lots of code ordering ports in module declarations inputs first:

module do_something(     input wire clk_in,     input wire a_in,     input wire b_in,     output reg val_out); .... endmodule

(almost same way i'm used when programming in c/c++: inputs first, outputs).

however i've seen examples opposite order of parameters (output first, inputs last).

i hope isn't dumb question:

is there recommendation/best practice prefer 1 on other? far i'd stick "inputs first" wanted ask before forming bad habit.

usually clocks , resets first. followed io grouped function if it's large module has more 1 'thing' going on @ once. within group order inputs first , outputs, other way fine.

ultimately it's matter of style important thing be consistent. pick style , stick it.


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